Solid-state area image sensors of the interline type normally include an array having columns and rows of photodetectors. A so-called vertical shift register is located adjacent to each of the columns of photodetectors, and charge carriers generated in the photodetectors are transferred to the vertical shift registers during each frame time. The entire detected image is then shifted down in unison and transferred to a horizontal shift register one line at a time. The horizontal shift register delivers the charge carriers in each line to signal processing circuitry before the next line is shifted in.
Charge coupled devices often referred to as "CCDs" are photosensitive devices and used primarily for electronic imaging. Image sensors can also use photodiodes associated with vertical CCDs. This is called an interline image sensor. Each photodiode on the image sensor is called a pixel. The image resolution clocked out of the sensor is improved by increasing the number pixels on the sensor. The frame rate of emptying a sensor is inversely proportional to the number of sensor pixels and directly proportional to the speed of horizontal clocks. The speed at which these sensors can be clocked out depends on a number of parameters. The frame rate is typically increased by providing multiple horizontal shift registers.
As shown in FIG. 1, there is a prior art design which includes two horizontal shift registers 20 and 22. There is shown an image sensor 10 which is coupled to the two horizontal shift registers. Image sensor 10 includes an imaging region 12 which has photosensitive elements 14 arranged in columns and rows. These photosensitive elements can typically be photodiodes. Adjacent each column of photosensitive elements 14 is a vertical shift register 15 for receiving charge carriers from the photosensitive elements 14 and transferring the charge carriers out of the imaging region 12. The charge carriers are transferred from imaging region 12 to the two horizontal shift registers 20 and 22. Shift registers 15, 20, and 22 are charge-coupled devices (CCDs). Charge carriers from the imaging region 12 are transferred into horizontal shift register 20, one row at a time. From horizontal shift register 20, the row of charge carriers can be shifted into the horizontal shift register 22 so that another row of charge carriers can be shifted into the horizontal shift register 20. When both horizontal shift registers 20 and 22 are full, the charge carriers can be shifted out to an output circuit (not shown) through buffer amplifiers 24 and 26. For a further description of an image sensor having multiple horizontal shift registers, see commonly assigned U.S. Pat. No. 4,949,183, the disclosure of which is incorporated by reference herein.
Charge is transferred downwardly from the image sensor, a row of pixels at a time, under the control of vertical clock driver signals V.sub.1 and V.sub.2 (FIG. 1). The vertical clock driver signal V.sub.1 is used to transfer a row of pixels, in parallel, into the first horizontal shift register 20. Horizontal clock signals H.sub.1A and H.sub.1B are used to shift pixel information, a pixel at a time within horizontal shift registers 20 and 22. The vertical clock V.sub.2 is used to transfer a line of pixels from the horizontal shift register 20 into the horizontal shift register 22. In order to help facilitate this transfer with a minimum amount of charge loss, the horizontal clock driver of the present invention signal H.sub.1B has three levels. The third or highest level, as will be seen, is used to aid in that transfer.
Normally, the horizontal shift registers 20 and 22 transports the charge, pixel by pixel, to the output buffer amplifiers 24 and 26 by electrodes. These electrodes are electrically connected to the horizontal clock driver signals H.sub.2 and H.sub.1A and are fed to electrodes on the horizontal shift register 20. The second horizontal shift register 22 transports the charge, pixel by pixel, to the output buffer amplifier 26 in a similar manner under the control of the horizontal clock signal H.sub.1B. The charge is transferred into the second horizontal shift register 22 from the first horizontal shift register 20 by changing the potential levels (clock levels) on signals H.sub.1A and H.sub.1B, such that potential of H.sub.1A is more negative than the potential of H.sub.1B. These clock signals normally operate in two levels, namely low level and high level. For transferring the charge from the first horizontal shift register 20 to the second horizontal shift register 22, the present invention employs a third level signal is provided by the H.sub.1B clock signal, ensuring there will be better charge efficiency.
In order to increase the frame transfer rate, the sensor's horizontal shift registers are clocked out as fast as possible. At high speed, the driver circuit needs to provide high edge current. There are some clock drivers which can drive CCDs up to 40 megahertz with a clock signal voltage swing of 10 volts. Discrete component clock drivers using high speed switching transistors can operate up to 40 megahertz. For the sensors with the kind of architecture shown in FIG. 1, there is a need for a third level on the horizontal clock driver signal H.sub.1B which also drives the sensor at 40 megahertz.
Heretofore, in some arrangements, three level vertical clock driver signals have been used. The advantage of three level arrangement is that the highest level can be used to aid in transfer of charge and is frequently used for transferring charge from a photodiode to a vertical shift register. These vertical clock signals are normally operated in the kilohertz range with a pulsewidth of 1-10 microseconds. However, this arrangement has a number of difficulties associated with it. The most important being that it can not be used for high speed clock transfer. High speed clock transfer is achieved by high speed horizontal clock drivers and typically operates between 10-40 megahertz.